The present invention relates to a nonvolatile semiconductor memory device and, more particularly, to a nonvolatile semiconductor memory device which writes data by the self-boost write method.
Recently, a demand for nonvolatile semiconductor memory device has greatly increased because these memories have the advantages that, e.g., data is not erased even when the power supply is turned off. In a flash memory which is an electrically simultaneously erasable nonvolatile semiconductor memory device, the memory cell can be formed by one transistor unlike in a two-transistor type byte nonvolatile semiconductor memory device. As a consequence, the memory cell shrinks, so the possibility of use of this flash memory as, e.g., a substitute for a large-capacity magnetic disk and the like is being explored.
Among other flash memories, a NAND EEPROM is known as a memory particularly advantageous to increase the degree of integration. This memory has the following structure. That is, a plurality of memory cells are arrayed in the column direction, and the source and drain of each pair of adjacent cells are connected. This connection forms a unit cell group (NAND cell) in which a plurality of memory cells are connected in series. This unit cell group is connected as a unit to a bit line.
A memory cell has a stacked gate structure in which a floating gate which commonly functions as a charge storage layer and a control gate electrode are stacked. Such memory cells are integrated in a matrix manner in a p-type well which is formed in a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to a bit line via a selector gate. The source side of the NAND cell is connected to a source line (reference potential line) via a selector gate. The control gate of each memory cell is connected to a word line extending in the row direction.
Data is written in or erased from the NAND cell by injecting or releasing electrons into or from the floating gate of a memory cell. Data erase is performed as follows. For example, in a whole memory cell array, all word lines are set to 0V, and an erase voltage Vee of about 20V is applied to the substrate or well, thereby causing all memory cells to release electric charge from their floating gates to the substrate. Consequently, all memory cells are erased to a "1" data state in which the threshold value is negative. If a plurality of memory cell array blocks are present, data erase is sometimes performed in units of blocks. If this is the case, selected blocks are processed under the above conditions, and all word lines float in non-selected blocks.
Data write is performed in the following manner. A write voltage Vpp of about 20V is applied to a selected word line to which a memory cell in which data is to be written is connected. An intermediate voltage Vpass is applied to other non-selected word lines in the NAND cell. Also, the channel potential of the memory cell connected to the selected word line is controlled in accordance with whether the write data is "0" or "1". That is, if the write data is "0", 0V of the bit line is transferred to the channel of the memory cell to inject electrons into the floating gate by a tunnel current. Accordingly, the threshold value of the memory cell becomes positive. On the other hand, if the write data is "1", the channel potential of the memory cell is set through the bit line to an intermediate potential by which no tunnel injection takes place. Consequently, the threshold value of the memory cell is kept low and negative.
Data read is performed by applying 0V to a selected word line and an intermediate voltage by which a memory cell is turned on to the rest of word lines in the NAND cell regardless of whether the data is "0" or "1", and detecting through the bit line whether the NAND cell is turned on.
In writing data into a NAND EEPROM as described above, if low-voltage driving is realized a column peripheral circuit connected to a bit line can be constructed by Vcc transistors. This decreases the area of this peripheral circuit. In consideration of this advantage, the self-boost write method in which only the channel potential of a memory cell in which "1" data is to be written is sufficiently raised by using capacitive coupling has been proposed and put into practical use. A write performed by this self-boost write method will be described below.
FIG. 1 is an equivalent circuit diagram of a memory cell unit of a conventional NAND EEPROM. Reference symbols BL, SG, CG, and SL denote a bit line, selector gate line, word line, and source line, respectively.
If data write simultaneously performed for a plurality of memory cells in the row direction is a common write, data is sequentially written from the memory cell farthest from the bit line BL. If the data write is a random write, data is written in an arbitrary memory cell between the bit line BL and the source line SL.
In either case, 0V is applied to a selector gate line SG2 near the source line SL to switch off a selector gate transistor. A bit line BL to which a NAND cell having a memory cell in which "0" data is to be written is connected is set to a write selection potential of 0V. A bit line BL to which a NAND cell having a memory cell in which "1" data is to be written is connected is set to a write non-selection potential, more specifically, a potential higher than that of a selector gate line SG1 near the bit line BL or a potential which is lower than that of the selector gate line SG1 but by which a selector gate transistor is cut off. Note that a predetermined positive voltage is supplied to the source line SL to sufficiently cut off a selector gate transistor near the source line SL.
When the write voltage Vpp or the intermediate voltage Vpass is applied to a word line CG of a selected block in this state, memory cells are turned on when the voltage pulse rises. As a consequence, 0V is transferred to the channel of the NAND cell connected to the bit line BL set at 0V as the write selection potential. Accordingly, electrons are injected by a tunnel current into the floating gate of a memory cell connected to a selected word line, and "0" data is written in the cell.
In the NAND cell connected to the bit line BL set at the write non-selection potential, an initial potential obtained by subtracting the threshold value of the selector gate transistor from the potential of the bit line BL is transferred to the channel of the NAND cell from the bit line BL via the selector gate transistor. After that, the selector gate transistor near the bit line is cut off to float the channel of the NAND cell. Therefore, when the write voltage Vpp or the intermediate voltage Vpass is applied to the word line CG of the selected block, the capacitive coupling between these word line and NAND cell channel boots the channel potential of the NAND cell from the initial potential as described above. Consequently, the floating gate of a memory cell connected to a selected word line is also set to a write inhibit voltage by which no tunnel injection occurs. That is, "1" data by which the threshold value of the memory cell is kept negative is written.
A write inhibit voltage actually obtained by the self-boost write method is calculated below by taking account of the write timings in this method. Assume that the potential of the bit line BL is set to 0V or a power-supply voltage Vcc (e.g., 3.3V) in accordance with write data, Vcc is supplied to the source line SL and the selector gate line SG1 near the bit line BL, and 0V is supplied to the selector gate line SG2 near the source line SL. If the write voltage Vpp (e.g., 20V) and the intermediate voltage Vpass (e.g., 10V) are applied to a selected word line CG and a non-selected word line, respectively, of a selected block, the floating channel of the NAND cell is booted to a write inhibit voltage Vch. This write inhibit voltage Vch is represented by
Vch=Vsg-Vsgth(Vchinit)+Cr1(Vpass-Vpassth(Vchinit))+Cr2(Vpp-Vpassth(Vchinit ))
(where Vsg is the potential of the selector gate line SG1 near the bit line BL, Vsgth (Vchinit) is the threshold value of a selector gate transistor near the bit line BL when the initial channel potential of the NAND cell is Vchinit, Cr1 and Cr2 are the channel boot ratios, Cr1 being the ratio of the total channel capacitance to the gate-channel capacitance of all memory cells connected to non-selected word lines, and Cr2 being the ratio of the total channel capacitance to the gate-channel capacitance of a memory cell connected to a selected word line, and Vpassth (Vchinit) is the gate potential necessary to turn on a memory cell when the NAND cell channel potential is Vchinit.)
The above equation shows that the conditions by which memory cells and selector gate transistors are formed have large influence on the write inhibit voltage Vch in the self-boost write method. That is, the channel initial potential Vchinit of the NAND cell and the channel boot ratios Cr1 and Cr2 in the above equation largely depend upon the concentration profile of the source drain diffusion layer of the memory cell or selector gate transistor, the impurity concentration profile of the substrate or well, and the profile of ion implantation performed for the channels of the memory cell and selector gate transistor. Therefore, if these profiles change, no sufficient write inhibit voltage Vch can be obtained in some cases in a memory cell in which "1" data is to be written. Consequently, the threshold value of the memory cell in which "1" data is to be written changes to lead to write error.
As described above, the self-boost write method has the problem that variations in the various characteristics such as the impurity profiles of memory cells and selector gate transistors degrade the memory cell write error characteristics. To solve this problem, Symp. VLSI Technology Dig. Tec. Papers, June 1996, pp. 236-237 and pp. 238-239 has recently reported a technique which sufficiently raises the channel potential of a memory cell in which "1" data is to be written by using a conductor constructed of a booster plate electrode, thereby improving the memory cell write error characteristics.
FIG. 2 is a partially cutaway perspective view showing the arrangement of a NAND EEPROM having this booster plate electrode. As shown in FIG. 2, this NAND EEPROM is characterized in that a booster plate electrode 76 is formed via a plate oxide film 75 on a stacked gate structure obtained by forming a floating gate 72 and a control gate 74 on the surface of a substrate 70 via a gate insulating film 71 and an ONO film 73, respectively. Writes, erases, and reads are generally identical with those of the aforementioned NAND EEPROM except that the booster plate electrode 76 is set at the same write voltage Vpp as a selected word line when data is written and supplied with 0V when data is erased.
The reference cited above indicates that in this NAND EEPROM having the booster plate electrode, the write voltage Vpp and the intermediate voltage Vpass applied to selected and non-selected word lines of a selected block when data is written can be lowered to 13V and Vcc, respectively, for the reasons explained below. That is, since the booster plate electrode is capacitively coupled with the control gate via the plate oxide film, the essential capacitive coupling ratio during data write increases. Additionally, the booster plate electrode is also capacitively coupled with the source and drain of each memory cell in a NAND cell via the plate oxide film, so the floating channel potential of the NAND cell is booted by the booster plate electrode.
More specifically, a NAND EEPROM having a booster plate electrode uses the capacitive coupling between the control gate and booster plate electrode and the channel of a NAND cell and hence can raise the channel potential of a memory cell in which "1" data is to be written to a sufficiently high write inhibit voltage Vch. Accordingly, it is possible to suppress variations in the threshold value of a memory cell in which "1" data is to be written and avoid degradation of the memory cell write error characteristics in the self-boost write method. Also, when data write is performed a sufficiently high write inhibit voltage Vch can be obtained in a memory cell in which "1" data is to be written without excessively raising the intermediate voltage Vpass of a non-selected word line in a selected block. As a consequence, write error can also be effectively prevented in a memory cell connected to a non-selected word line near a NAND cell to the channel of which 0V is transferred from a bit line BL.
In this NAND EEPROM, however, to allow the booster plate electrode to is capacitively coupled with the source and drain of each memory cell in a NAND cell via the plate oxide film, a conductor layer serving as the booster plate electrode must be buried very close to the source and drain between adjacent memory cells each having a stacked gate structure after these memory cells are formed. If the spacing between a plurality of word lines in a NAND cell is narrowed to increase the aspect ratio of a memory cell having the stacked gate structure, it becomes very difficult to bury the conductor layer serving as the booster plate electrode between memory cells. This makes this NAND EEPROM very unsuitable to further shrinkage of the memory cell array.
In a NAND EEPROM having a booster plate electrode as described above, a sufficiently high write inhibit voltage Vch can be obtained, and the intermediate voltage Vpass of a non-selected word line in a selected block can be lowered. Accordingly, it is possible to wide the write error margin by eliminating degradation of the write error characteristics which is a problem in the self-boost write method. However, this NAND EEPROM is totally unsuitable to further shrinkage of the memory cell array.